1. Field of the Invention
The present invention generally relates to a DC--DC converter unit, and particularly to a DC--DC converter unit in which a synchronous rectifying circuit is advanced so that the conversion efficiency is improved and the miniaturization can be achieved.
2. Description of the Related Art
A conventional DC--DC converter unit is formed as shown in FIG. 1. This DC--DC converter unit is a forward-type converter. Referring to FIG. 1, a primary sided of a power conversion transformer T is applied with a DC voltage Vin and connected with a smoothing capacitor Cin. A field effect transistor (FET) which is operated as a switching device is serially connected to a primary winding N1 of the power conversion transformer T. The FET is symbolized by Q1. A control circuit 1 detects an output voltage and supplies a PWM signal to the switching device Q1 so that the output voltage is maintained at a constant value. The PWM pulses from the control circuit 1 is supplied to the gate of the switching device (FET) Q1.
A secondary winding N2 of the power conversion transfer T is connected with diodes D1 and D2 which are used for the full-wave rectification. The rectified DC voltage is output from a point at which cathodes of the diodes D1 and D2 are connected to each other. The DC voltage is smoothed by a choke coil L1 and a capacitor Co and power is supplied to a load 2. The diode D1 is in a conductive state when the switching device Q1 is in an on-state. The diode D1 is named a rectifying diode. The diode D2 is in a conductive state when the switching device Q1 is in an off-state. The diode D2 is named a commutating diode. The output voltage (the DC voltage) is monitored. The detected output voltage Vo is then fed back to the control circuit 1.
The circuit having the above structure is operated as follows.
Due to the on-voltage signal from the control circuit 1, the switching device Q1 is turned on. At this time, an input voltage Vin is applied to the primary winding of the power conversion transformer T. A voltage corresponding to a winding ratio is generated from the secondary winding. The power corresponding to this voltage is supplied to the load 2 through a smoothing filter (the diode D1, the choke coil L1 and the capacitor Co).
On the other hand, when the switching device Q1 is turned off, the smoothing coil (the choke coil) L1 is operated as a power source, so that the power is supplied to the load 2 through the smoothing filter (the choke coil L1, the capacitor Co and the diode D2). The operating waveforms in respective points are shown in FIG. 2. Referring to FIG. 2, a PWM control pulse (a), a drain-source voltage Vds of the switching device Q1 (b), a current Id flowing through the drain of the switching device Q1 (c), a primary winding voltage Vt1 of the power conversion transformer T (d), a secondary winding voltage Vt2 of the power conversion transformer T (e), a voltage Vd1 supplied between both ends of the rectifying diode D1 (f), a current Id1 flowing through the rectifying diode D1 (g), a voltage Vd2 supplied between both ends of the commutating diode D2 (h) and a current Id2 flowing through the commutating diode D2 are provided. The drain-source voltage Vds of the switching device Q1 has waveform parts which are rounded as shown by (b) in FIG. 2. The rounded waveform parts are caused by a reset voltage (the LC resonance) based on transformer excitation energy.
This unit is operated at a constant switching frequency (the period t=t.sub.on +t.sub.off). The output voltage Vo is detected and fed back to the control circuit 1 which carries out the PWM control so that the output voltage is maintained at a constant value. The control circuit 1 controls the on-width of the switching device Q1 operated at the constant switching frequency so that the output voltage is controlled. The output voltage Vo is represented by the following equation. EQU Vo=(N2/N1).multidot.D.multidot.Vin (1)
In the above equation, Vin is the input voltage, N1 is the number of turn of the primary winding of the power conversion transformer and N2 is the number of turn of the secondary winding of the power conversion transformer. D is a time ratio represented by t.sub.on /t. The period t is defined by t=1/f (f is the frequency) and has a constant value.
The above type of unit is very simple and generally used. In the recent years, miniaturization and high-efficiency of the power supply are desired. Thus, the loss factor in the rectifying diodes D1 and D2, which appears as about 30% through 40%, has to be improved. Providing that the forward voltage Vf (about 1 volt) is generated by each of the rectifying diodes D1 and D2 and the current I flows through each of the diodes D1 and D2, the power loss of Vf.multidot.I is generated. In the recent years, Schottky barrier diodes having a low forward voltage are used as the rectifying diodes D1 and D2.
To further improve the power loss, the use of a MOS-FET having a low ON-state resistance instead of each of the rectifying diodes D1 and D2 has been examined. Providing that a power supply has a output characteristic of 5 volts (V)/10 amperes (A), the power loss is as follows.
In a case where the Schottky barrier diodes are used, since the forward voltage of the diode is about 0.4 volts (V), the power loss Ps is estimated as EQU Ps=Vf .times.Io=0.4(V).times.10(A)=4 [W].
In a case where the MOS-FET having the low ON-state resistance is used, the ON-state resistance Rds of the MOS-FET is about 10 m.OMEGA., the power loss Ps is estimated as EQU Ps=Rds.times.Io.sup.2 =10m.OMEGA..times.10.sup.2 A=1 [W].
In the later case, the power loss generated in the output rectifying diode portion is one fourth as large as that in the former case.
FIG. 3 shows a conventional unit (the power conversion portion) in which FETs are used as the rectifying circuit. In FIG. 3, those parts which are the same as those shown in FIG. 1 are given the same reference numbers. A rectifying FET Q2 is substituted for the rectifying diode D1 and a commutating FET Q3 is substituted for the commutating diode D2. Each of the FETs has a parasitic diode as shown by a dashed line in FIG. 3.
Operating waveforms of the unit as described above are shown in FIG. 4. In this unit, the gate of each of the FETs Q2 and Q3 are driven by using the voltage generated by the secondary winding of the power conversion transformer T so that each of the FETs is turned on and off. FIG. 4 shows the voltage generated by the secondary winding of the power conversion transformer T and the operating waveforms of the FETs Q2 and Q3. That is , in FIG. 4, the voltage Vt2 generated by the secondary winding of the power conversion transformer T (a), the gate voltage Vgs1 of the FET Q2 (b), the drain current Id1 flowing through the FET Q2 (c), the gate voltage Vgs2 of the FET Q3 (d) and the drain current Id2 flowing through the FET Q3 are provided.
When the switching device Q1 is in the on-state, the voltage (A) is generated by the secondary winding of the power conversion transformer T as shown in FIG. 4(a). The voltage (A) is supplied between the gate and source of the FET Q2 through a loop including a leading end of the secondary winding of the power conversion transformer T, the gate of the FET Q2, the source of the FET Q2, the parasitic diode of the FET Q2 and a trailing end of the secondary winding of the power conversion transformer T. Due to the voltage (A), the FET Q2 is turned on and the drain current Id1 flows as shown in FIG. 4(c).
On the other hand, when the switching device Q1 is turned off, the polarity of the voltage generated by the secondary winding of the power conversion transformer T is inverted as shown by (B) in FIG. 4(a). At this time, the voltage (B) is supplied between the gate and source of the FET Q3 through a loop including the trailing end of the secondary winding of the power conversion transformer T, the gate of the FET Q3, the source of the FET Q3, the parasitic diode of the FET Q3 and the leading end of the secondary winding of the power conversion transformer T. Due to the voltage (B), the FET Q3 is turned on and the drain current Id2 flows as shown in FIG. 4 (e).
In the conventional unit using the FETs, there is a term (C) in which no voltage is generated by the secondary winding of the power conversion transformer T in each period as shown in FIG. 4 (a). In the term (C), since no voltage is supplied to the FET Q3, the gate of the FET Q3 is in a floating state so that the FET Q3 can not be turned on. Thus, a load current completely flows through the parasitic diode.
The forward voltage of the parasitic diode is not less than 1 volt (V), so that a large amount of power loss is generated and the high efficiency is prevented. Further, since the parasitic diode has a large reverse recovery time, a state where a short-circuit current flows through the parasitic diode is maintained in a moment that the switching device Q1 is turned on in the next period. In this moment, the short-circuit current flows the switching device Q1, so that the loss generated by the switching device Q2 is increased.
In addition, to eliminate the above disadvantage, the Schottky barrier diode having the low forward voltage has to be connected to the FET in parallel. As a result, the production cost of the unit may be increased and the unit may be enlarged.